A Double-Pulsed Set-Conditional-Reset Flip-Flop
نویسنده
چکیده
A new flip-flop design using a double-pulsed static latch is presented. The flip-flop has only a single stage of logic in the critical path and as a result is up to three times faster than the fastest previously known flip-flops, while consuming approximately the same energy as the lowestpower flip-flops. The flip-flop has asymmetric timing properties which make it a good match to skewed logic styles. A novel dual-pulse generator further reduces power requirements.
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